Conventional polishing systems and polishing methods typically are not entirely satisfactory at planarizing substrates. In particular, polishing compositions and polishing pads can have less than desirable polishing rates, and their use in chemically-mechanically polishing surfaces can result in poor surface quality. Because the performance of, for example, a semiconductor water is directly associated with the planarity of its surface and its low defectivity, it is crucial to use a polishing composition and method that results in a high polishing efficiency, uniformity, and removal rate, and leaves a high quality polish with minimal surface defects.
One problem with chemical mechanical polishing is that formulations are designed for controlled substrate removal rates, where the maximum practical removal rate is about 6000 Angstroms per minute, as at rates above this planarity suffers and it is difficult to stop the process at the precise time. However, in certain manufacturing processes, there is occasionally large excesses of metal put on a wafer, and removing these excesses with the formulations developed for very controlled substrate removal at intermediate rates creates an economically unfavorable processing time. Large excesses of metal, e.g., copper, are found in for example copper oversputter methodologies. Overfilled and/or oversputtered substrates are also well known in the art. An example of these substrates, as well as issues associated with their fabrication, can be found in U.S. Pat. No. 4,789,674, which is hereby incorporated by reference in its entirety.
The difficulty in creating an effective polishing system for semiconductor wafers stems from the complexity of the semiconductor wafer. Semiconductor wafers are typically composed of a substrate, on which a plurality of transistors has been formed. Integrated circuits are chemically and physically connected into a substrate by patterning regions in the substrate and layers on the substrate. To produce an operable semiconductor wafer and to maximize the yield, performance, and reliability of the wafer, it is desirable to polish select surfaces of the wafer without adversely affecting underlying structures or topography. In fact, various problems in semiconductor fabrication can occur if the process steps are not performed on wafer surfaces that are adequately planarized.
A variety of chemical mechanical polishing and/or residue removal compositions and processes suitable for integrated circuit fabrication have been developed and marketed by EKC Technology, Inc. (hereinafter “EKC”), the assignee of the present application. Some of these compositions and processes are also useful for removing photoresist, polyimide, or other polymeric layers from substrates in integrated circuit fabrication, and EKC has also developed a variety of compositions and processes specifically for removing such polymeric layers from substrates in integrated circuit fabrication. Additionally, EKC has developed a variety of compositions and processes to selectively remove specific substrate compositions from a substrate surface at a controlled rate. Such compositions and processes are disclosed in the following commonly assigned issued patents:
U.S. Pat. No. 6,367,486 to Lee et al., which issued on Apr. 9, 2002, entitled Ethylenediaminetetraacetic acid or its ammonium salt semiconductor process residue removal process;
U.S. Pat. No. 6,313,039 to Small et al., which issued on Nov. 6, 2001, entitled Chemical mechanical polishing composition and process;
U.S. Pat. No. 6,276,372 to Lee, which issued on Aug. 21, 2001, entitled Process using hydroxylamine-gallic acid composition;
U.S. Pat. No. 6,251,150 to Small et al., which issued on Jun. 26, 2001, entitled Slurry composition and method of chemical mechanical polishing using same;
U.S. Pat. No. 6,248,704 to Small et al., which issued on Jun. 19, 2001, entitled Compositions for cleaning organic and plasma etched residues for semiconductors devices;
U.S. Pat. No. 6,242,400 to Lee, which issued on Jun. 5, 2001, entitled Method of stripping resists from substrates using hydroxylamine and alkanolamine;
U.S. Pat. No. 6,235,693 to Cheng et al., which issued on May 22, 2001, entitled lactam compositions for cleaning organic and plasma etched residues for semiconductor devices;
U.S. Pat. Nos. 6,187,730 and 6,221,818, both to Lee, which issued on Feb. 13, 2001 and on Apr. 24, 2001, respectively, entitled Hydroxylamine-gallic compound composition and process;
U.S. Pat. No. 6,156,661 to Small, which issued on Dec. 5, 2000, entitled Post clean treatment;
U.S. Pat. No. 6,140,287 to Lee, which issued on Oct. 31, 2000, entitled Cleaning compositions for removing etching residue and method of using;
U.S. Pat. No. 6,121,217 to Lee, which issued on Sep. 19, 2000, entitled Alkanolamine semiconductor process residue removal composition and process;
U.S. Pat. No. 6,117,783 to Small et al., which issued on Sep. 12, 2000, entitled Chemical mechanical polishing composition and process;
U.S. Pat. No. 6,110,881 to Lee et al., which issued on Aug. 29, 2000, entitled Cleaning solutions including nucleophilic amine compound having reduction and oxidation potentials:
U.S. Pat. No. 6,000,411 to Lee, which issued on Dec. 14, 1999, entitled Cleaning compositions for removing etching residue and method of using; U.S. Pat. No. 5,981,454 to Small, which issued on Nov. 9, 1999, entitled Post clean treatment composition comprising an organic acid and hydroxylamine;
U.S. Pat. No. 5,911,835 to Lee et al., which issued on Jun. 15, 1999, entitled Method of removing etching residue;
U.S. Pat. No. 5,902,780 to Lee, which issued on May 11, 1999, entitled Cleaning compositions for removing etching residue and method of using;
U.S. Pat. No. 5,891,205 to Picardi et al., which issued on Apr. 6, 1999, entitled Chemical mechanical polishing composition;
U.S. Pat. No. 5,672,577 to Lee, which issued on Sep. 30, 1997, entitled Cleaning compositions for removing etching residue with hydroxylamine, alkanolamine, and chelating agent;
U.S. Pat. No. 5,482,566 to Lee, which issued on Jan. 9, 1996, entitled Method for removing etching residue using a hydroxylamine-containing composition;
U.S. Pat. No. 5,399,464 to Lee, which issued on Mar. 21, 1995, entitled Triamine positive photoresist stripping composition and post-ion implantation baking;
U.S. Pat. No. 5,381,807 to Lee, which issued on Jan. 17, 1995, entitled Method of stripping resists from substrates using hydroxylamine and alkanolamine;
U.S. Pat. No. 5,334,332 to Lee, which issued on Aug. 2, 1994, entitled Cleaning compositions for removing etching residue and method of using;
U.S. Pat. No. 5,279,771 to Lee, which issued on Jan. 18, 1994, entitled Stripping compositions comprising hydroxylamine and alkanolamine;
U.S. Pat. No. 4,824,763 to Lee, which issued on Apr. 25, 1989, entitled Triamine positive photoresist stripping composition and prebaking process; and
U.S. Pat. No. 4,395,348 to Lee, which issued on Jul. 26, 1983, entitled Photoresist stripping composition and method.
The entire disclosures of all of the aforementioned EKC publications are incorporated herein for all purposes by express reference thereto. The compositions described therein have achieved substantial success in integrated circuit fabrication applications.
Compositions and methods for planarizing or polishing the surface of a substrate, especially for chemical-mechanical polishing (CMP), are well known in the art. Polishing compositions (also known as polishing slurries if the composition contains an abrasive) typically contain an abrasive material and an oxidizer in an aqueous solution, and are applied to a surface by contacting the surface with the slurry disposed between a moving polishing pad which exerts pressure as well as providing horizontal movement. Typical abrasive materials include silicon oxide, cerium oxide, aluminum oxide, zirconium oxide, and tin oxide. Alternatively, the abrasive material may be incorporated into the polishing pad. U.S. Pat. No. 5,489,233 discloses the use of polishing pads having a surface texture or pattern, and U.S. Pat. No. 5,958,794 discloses a fixed abrasive polishing pad. All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to the same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein.
In cases where the substrate is associated with integrated circuit manufacture but is not a semiconductor wafer (e.g., a substrate linking multiple wafers or chips, such as one that can provide a conductive link between such wafers/chips through strategically-placed, interconnected metal-containing conduits linking otherwise non-conductive surfaces), surface planarity, regularity, and/or low defectivity constraints may be lessened.